Integrating Physics-based Manufacturing-aware Modeling Tools of IC CAD Framework
C. Fred Higgs, Mechanical Engineering and Computer & Electrical Engineering
As the size of features in CMOS integrated circuits shrink below the 50nm- node level, the ability to predict the effects of chemical mechanical polishing (CMP) for planarization of thin films has become increasingly important. Commercial software packages in use for IC design, such as Cadence, do not consider the surface irregularities that are introduced during each CMP step in the fabrication process. These irregularities can have significant effects on the performance of the circuit, including both power consumption and clock speed. The student on this project will help employ the state-of-art physics-based model for modeling the effects of CMP in circuit simulations. This method may be used to better predict circuit performance based on initial CAD designs of IC layout, leading to better device yield after fabrication. This project is at the cutting-edge of the IC design for manufacturing (DFM) process flow. The student who master this project will be coveted because he/she will sit at the interface of IC design and manufacturing.
Skills needed: Senior standing in ECE; Taking or completed 18-322 (Analysis and Design of Digital Integrated Circuits).
Contact: Prof. C. Fred Higgs III (email: higgs@cmu.edu)
Higgs Lab: http://www.me.cmu.edu/faculty1/higgs
Ph.: 8-2486
Companies/Industries that have or are likely to approach professor for students to hire: Intel, DFM Industry (Cadence, Synopsys, PDF Solutions, Mentor Graphics, etc.), IBM.